61012R-ASIC Engineer 2

ASIC Verification Engineer 2

Organization: 

Juniper is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. At Juniper Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting edge networking chips used to build world-class routers and switches. 

Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest possible density networking chips. 

As part of our fast-paced chip design group, you will become an expert in building high-speed ASICs, from specifications to final netlist. You pick and choose where you want to work – design, verification or timing closure/PD. As you are getting started in your career, we will let you explore your passions here. 

Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team.  Thus, you set your own limits for learning, achievements and rewards. 

Responsibilities:

You will be exposed to the latest verification methodologies such as UVM and you will enable complex feature verification suites. 

• You will start with a functional specification of a module and produce a detailed test plan to verify the module – do not worry, you will have guidance from our senior engineers on how to go about this if you haven’t done this before. 


• You will build the module level test bench using System Verilog/UVM


• You will write tests according to the test plan and find bugs in the module. You will be responsible for making sure your module is fully functional. 


• You will learn and use state of the art tools for doing formal verification, code coverage analysis, gate sims, and more. 


• You will also get a chance to be part of full chip/sub-system and emulation testing – which gives you exposure to the entire functionality of the chip/system. 


• You get to participate in asic validation in the lab if you are passionate about making the chip come alive. 

 
Required and Desired Skills:

• Bachelor’s degree required, Master’s strongly desired in Electrical Engineering or Computer Science/Engineering


• Strong analytical/ problem solving skills.


• Should have taken courses in digital logic design and design validation/UVM (if offered). 


• Strong coding skills in Verilog/System Verilog through courses and projects


• Experience in constrained-random verification with methodologies such as UVM is a plus. 


• Knowledge of Computer Architecture/networking protocols and machine learning through graduate level courses is a plus.


• Knowledge of Perl/Python/C/C++ is a strong plus. 


• Excellent written and verbal communications skills is good to have.

Minimum Salary: $102,400.00

Maximum Salary:$147,200.00

The pay range for this position is expected to be between $102,400.00 and $147,200.00/year; however, the base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. The total compensation package for this position also includes medical benefits, 401(k) eligibility, vacation, sick time, and parental leave. Additional details of participation in these benefit plans will be provided if an employee receives an offer of employment.

If hired, employee will be in an “at-will position” and the Company reserves the right to modify base salary (as well as any other payment or compensation program) at any time, including for reasons related to individual performance, Company or individual department/team performance, and market factors.

Juniper’s pay range data is provided in accordance with local state pay transparency regulations. Juniper may post different minimum wage ranges for permanent residency petitions pursuant to US Department of Labor requirements.