Advanced ASIC FPGA Verification Engineer

Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a
minimum of 3 years of relevant experience.

 

CLEARANCE REQUIREMENTS: 

Duties and Tasks:
• Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments
• Determines architecture, system simulation and detailed design approach
• Defines module interfaces and all aspects of device design and simulation
• Evaluates the process flow including but not limited to high level design, synthesis, place and route, timing and power utilization
• Creates test and simulation plans that establish functional criteria
• Verifies test results and analyzes performance
• May also review vendor capabilities, foundry technologies, device libraries and simulation tools
• Participates in the improvement of the ASIC/FPGA organizational processes
• Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle
• Contributes to the research and analysis of data, such as customer design proposal specifications, and manuals to determine feasibility of design or application
• Selects components and equipment based on analysis of specifications and reliability
• May provide leadership and/or direction to lower level employees
• Independently determines approach to solutions
• Contributes to the completion of major programs and projects
• Plans and executes project tasks for activities described above
Knowledge, Skills and Abilities:
• Proficient use and understanding of ASIC/FPGA engineering concepts, principles, and theories
• Proficient in the principles and techniques of ASIC/FPGA design
• Proficient understanding of ASIC/FPGA processes
• Proficient knowledge of other related disciplines
• Keeps abreast of technology trends
• Proficient awareness of business objectives and Engineering’s role in achieving
• Proficient in Microsoft Office applications
• Proficient in ASIC/FPGA design tools
• Proficient written and verbal communications skills
• Ability to think creatively
• Ability to multi-task
• Proficient skill in communicating issues, impacts, and corrective actions
• Proficient ability to recognize and clearly report information relevant to sound ASIC/FPGA design
• Proficient ability to develop and sell concepts and ideas
• Regular contact with senior levels of internal work groups
• Works under limited direction
• Contact with project leaders and other professionals within the Engineering department and with project teams across the company
• Some contact with external customers

• Experience with most, if not all, of the following languages and process are highly desired:

 

Key Responsibilities: 

The individual will be responsible for and participate in the ASIC/FPGA verification life cycle (requirements, environment architecture, implementation, and final test).  Will develop a skillset in System Verilog RTL coding and proficiency with Universal Verification Methodology (UVM).

 

This candidate must have an ability to operate in a team environment and learn new skills to accomplish the verification goals. 

 

Basic Qualifications for Verification Engineer:

• Experience with object-oriented programing
• Experience with scripting languages such as TK, Perl, or Python
• Familiarity with System Verilog is preferable
• Effective communicator with strong written and presentation skills
• Proficient and passionate about technical problem solving and debugging faults
• S. citizenship with the ability to obtain and maintain a security clearance

You will learn about:

• System Verilog UVM for verification
  • Testbench infrastructure (agents, drivers, monitors, interfaces, scoreboards, environments, etc.)
• Developing verification matrices to ensure coverage of requirements
• Developing functional coverage (covergroups, cover points) to measure test effectiveness
• Regression testing methods and defining regression test suits
• Managing regression simulations
• Tracking and resolving design bugs
• Siemens Verification tools (e.g., Questa and related products)

 

 

Key Words:  SystemVerilog, SystemVerilog Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random

 

This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.

USD $116,811.40 - USD $129,587.60 /Yr.

At General Dynamics Mission Systems, we rise to the challenge each day to ensure the safety of those that lead, serve, and protect the world we live in. We do this by making the world’s most advanced defense platforms even smarter. Our engineers redefine what’s possible and our manufacturing team brings it to life, building the brains behind the brawn on submarines, ships, combat vehicles, aircraft, satellites, and other advanced systems.

 

We pride ourselves in being a great place to work with this shared sense of purpose, committed to a diverse and exciting employee experience that drives innovation and creates a community where all feel welcome and a part of something amazing.

 

We offer highly competitive benefits and a flexible work environment where contributions are recognized and rewarded. To see more about our benefits, visit https://gdmissionsystems.com/careers/why-work-for-us/benefits

 

General Dynamics is an Equal Opportunity/Affirmative Action Employer that is committed to hiring a diverse and talented workforce. EOE/Disability/Veteran