Senior ASIC Design Engineer

Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual’s passions, growth, wellbeing and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

Why Ciena:

• You will be a member of a successful team working on the forefront of technological innovation focused on innovative technologies, flows and products.
• You will be working with, and learning from, industry recognized experts.
• Our team supports an inclusive, diverse and barrier-free work environment making for empowered and committed employees.
• We recognize the importance of well-being and offer programs and benefits to support and sustain the mental and physical health of our employees and their families.
• Great work deserves recognition. We have a robust recognition program, with ongoing and enhanced awards for exemplary performance.

How You Will Contribute:

Reporting to Director of ASIC Engineering, as a Senior ASIC Design Engineer, you will define block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.

• You will perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
• You will participate in synthesis, timing/power closure and FPGA/silicon bring-up.
• You will partake in test plan and coverage analysis of the block and SOC-level verification.

What Does Ciena Expect of You:

• Sense of urgency and accountability – what’s important to the customer is important to you; you make getting things done a priority.
• Diligence – you will deliver on objectives through meticulous, thorough, and comprehensive work.
• Agility – with an ability to flex between the strategic and tactical, you manage competing and ever-changing priorities and maintain a balanced and methodical approach to problem solving.
• Communication expertise – you possess the ability to tailor your message and ideas to the audience to ensure understanding and consensus.
• Problem solver – you possess the ability to analyze and methodically solve complex technical problems using engineering principles and approaches.
• Commitment to learning – you keep abreast of technology developments and are keen to share your knowledge with others.

The Must Haves:

• Bachelor of Science degree in Electrical Engineering coupled with proven experience ASIC development with Verilog.
• Experience with ASIC design verification, synthesis, timing/power analysis and DFT.
• Experience with modern SoC design architectures.
• ARM/MIPS type processor cores.
• Strong debug and lab experience.

Assets:

• Master of Science or PhD in Electrical Engineering.
• Knowledge of high performance and low power design techniques.
• Experience with Ethernet, Networking, and Data Communications
• · Knowledge of FPGA and emulation platforms. Knowledge of SOC architecture

Compensation and Benefits

The annual pay range for this position is $141,700 - 226,300 USD.

The annual pay range for this position in California is $157,900 - $252,200 USD.

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.